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Launched in June , Intel marketed the processors for enterprise servers and high-performance computing systems. In February , Intel released the final generation, Kittson , to test customers, and in May began shipping in volume.
In , Intel announced that Itanium CPU family production would terminate on January 30, , and shipments would cease as of July 29, In HP started to research an architecture that would exceed the expected limits of the reduced instruction set computer RISC architectures caused by the great increase in complexity needed for executing multiple instructions per cycle due to the need for dynamic dependency checking and precise exception handling.
One VLIW instruction word can contain several independent instructions , which can be executed in parallel without having to evaluate them for independence.
A compiler must attempt to find valid combinations of instructions that can be executed at the same time , effectively performing the instruction scheduling that conventional superscalar processors must do in hardware at runtime. HP researchers modified the classic VLIW into a new type of architecture, later named Explicitly Parallel Instruction Computing EPIC , which differs by: having template bits which show which instructions are independent inside and between the bundles of three instructions, which enables the explicitly parallel execution of multiple bundles and increasing the processors' issue width without the need to recompile; by predication of instructions to reduce the need for branches ; and by full interlocking to eliminate the delay slots.
EPIC was intended to provide the best balance between the efficient use silicon area and electricity, and the general-purpose flexibility. At the same time Intel was also looking for ways to make better ISAs. In Intel had launched the i , which it marketed for workstations, servers, and iPSC and Paragon supercomputers.
It differed from other RISCs by being able to switch between the normal single instruction per cycle mode, and a mode where pairs of instructions are explicitly defined as parallel so as to execute them in the same cycle without having to do dependency checking. Another distinguishing feature were the instructions for an exposed floating-point pipeline, that enabled the tripling of throughput compared to the conventional floating-point instructions.
Both of these features were left largely unused because compilers didn't support them, a problem that later challenged Itanium too. Without them, i's parallelism and thus performance was no better than other RISCs, so it failed in the market. Itanium would adopt a more flexible form of explicit parallelism than i had. In November HP approached Intel, seeking collaboration on an innovative future architecture. Yu declared: "If I were competitors, I'd be really worried.
If you think you have a future, you don't. Intel immediately issued a clarification, saying that P7 is still being defined, and that HP may contribute to its architecture. Later it was confirmed that the P7 codename had indeed passed to the HP-Intel processor. By early Intel revealed its new codename, Merced. HP believed that it was no longer cost-effective for individual enterprise systems companies such as itself to develop proprietary microprocessors, so it partnered with Intel in to develop the IA architecture, derived from EPIC.
Intel was willing to undertake the very large development effort on IA in the expectation that the resulting microprocessor would be used by the majority of enterprise systems manufacturers. HP and Intel initiated a large joint development effort with a goal of delivering the first product, Merced, in Merced was designed by a team of , which Intel later admitted was too inexperienced, with many recent college graduates.
Crawford Intel was the chief architect, while Huck HP held the second position. Early in the development HP and Intel had a disagreement where Intel wanted more dedicated hardware for more floating-point instructions. HP prevailed upon the discovery of a floating-pont hardware bug in Intel's Pentium. When Merced was floorplanned for the first time in mid, it turned out to be far too large, "this was a lot worse than anything I'd seen before", said Crawford.
The designers had to reduce the complexity and thus performance of subsystems, including the x86 unit and cutting the L2 cache to 96 KB. Later problems emerged with attempts to speed up the critical paths without disturbing the other circuits' speed.
Merced was taped out on 4 July , and in August Intel produced the first complete test chip. During development, Intel, HP, and industry analysts predicted that IA would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computing CISC architectures for all general-purpose applications.
By , it was apparent that the IA architecture and the compiler were much more difficult to implement than originally thought, and the delivery timeframe of Merced began slipping.
Intel announced the official name of the processor, Itanium , on October 4, Intel repositioned Itanium to focus on the high-end business and HPC computing markets, attempting to duplicate the x86's successful "horizontal" market i. Only a few thousand systems using the original Merced Itanium processor were sold, due to relatively poor performance, high cost and limited software availability.
HP and Intel brought the next-generation Itanium 2 processor to the market a year later. The Itanium 2 processor was released in July , and was marketed for enterprise servers rather than for the whole gamut of high-end computing.
It relieved many of the performance problems of the original Itanium processor, which were mostly caused by an inefficient memory subsystem by approximately halving the latency of each of the three levels of cache, while expanding the L2 cache from 96 to KB.
Floating-point data is excluded from the L1 cache, because the L2 cache's higher bandwidth is more beneficial to typical floating-point applications than low latency.
The L3 cache was now integrated on-chip, tripling in associativity and doubling in bus width. McKinley contains million transistors of which 25 million are for logic and million for L3 cache , measured It can be avoided by lowering the processor frequency to MHz.
The Opteron gained rapid acceptance in the enterprise server space because it provided an easy upgrade from x Under the influence of Microsoft, Intel responded by implementing AMD's x instruction set architecture instead of IA in its Xeon microprocessors in , resulting in a new industry-wide de facto standard. In Intel released a new Itanium 2 family member, codenamed Madison , initially with up to 1.
Both chips used a nm process and were the basis of all new Itanium processors until Montecito was released in July , specifically Deerfield being a low wattage Madison , and Fanwood being a version of Madison 9M for lower-end servers with one or two CPU sockets.
In November , the major Itanium server manufacturers joined with Intel and a number of software vendors to form the Itanium Solutions Alliance to promote the architecture and accelerate the software porting effort.
In early , due to the success of IBM's dual-core POWER4 , Intel announced that the successor of Madison, codenamed Montecito , will be delayed to so as to change it into a dual-core, thus merging it with the 90 nm Chivano project. It was supposed to feature Foxton Technology , a very sophisticated frequency regulator, which failed to pass validation and was thus not enabled for customers. Intel released the Itanium series, codenamed Montvale , in November , retiring the "Itanium 2" brand.
The original code name for the first Itanium with more than two cores was Tanglewood, but it was changed to Tukwila in late due to trademark issues.
Intel claimed "a lot more than two" cores and more than seven times the performance of Madison. In March , Intel disclosed some details of Tukwila, the next Itanium processor after Montvale, to be released in Tukwila would have four processor cores and would replace the Itanium bus with a new Common System Interface , which would also be used by a new Xeon processor.
The device uses a 65 nm process, includes two to four cores, up to 24 MB on-die caches, Hyper-Threading technology and integrated memory controllers. It implements double-device data correction , which helps to fix memory errors. QuickPath is also used on Intel x processors using the Nehalem microarchitecture, which possibly enabled Tukwila and Nehalem to use the same chipsets.
During the Hewlett-Packard Co. Oracle Corp. Information presented improvements in multithreading, resiliency improvements Intel Instruction Replay RAS and few new instructions thread priority, integer instruction, cache prefetching, and data access hints. Poulson was released on November 8, as the Itanium series processor.
It is the follow-on processor to Tukwila. It features eight cores and has a wide issue architecture, multithreading enhancements, and new instructions to take advantage of parallelism, especially in virtualization. The models are the following: [96] [99]. Intel had committed to at least one more generation after Poulson, first mentioning Kittson on 14 June In April , Intel, although it had not yet confirmed formal specifications, did confirm that it continued to work on the project.
Intel officially launched the Itanium series processor family on May 11, Intel announced that the series will be the last Itanium chips produced. The models are: []. In comparison with its Xeon family of server processors, Itanium was never a high-volume product for Intel.
Intel does not release production numbers. One industry analyst estimated that the production rate was , processors per year in According to Gartner Inc. It is unclear whether clustered servers counted as a single server or not. IDC reports that a total of , Itanium-based systems were sold from through A typical system uses eight or more Itanium processors. In addition, Intel offered a chassis that could be used by system integrators to build Itanium systems.
By , only HP supplied Itanium-based systems. Itanium is not affected by Spectre and Meltdown. Two generations of buses existed, the original Itanium processor system bus a.
The "Tukwila" Itanium processor model had been designed to share a common chipset with the Intel Xeon processor EX Intel's Xeon processor designed for four processor and larger servers. The goal was to streamline system development and reduce costs for server OEMs, many of which develop both Itanium- and Xeon-based servers. However, in , this goal was pushed back to be "evaluated for future implementation opportunities". In the times before on-chip memory controllers and QPI , enterprise server manufacturers differentiated their systems by designing and developing chipsets that interface the processor to memory, interconnections, and peripheral controllers.
Development of a chipset costs tens of millions of dollars and so represented a major commitment to the use of Itanium. The first generation of Itanium received no vendor-specific chipsets, only Intel's GX consisting of ten distinct chips. Addresses and data were handled by two different chips. There were many custom chipset designs for Itanium 2, but many smaller vendors chose to use Intel's E chipset.
Further expansion to 16 sockets was planned. HP has designed four different chipsets for Itanium 2: zx1, sx, zx2 and sx All support 4 sockets per chipset, but sx and sx support interconnection of up to 16 chipsets to create up to a 64 socket system. In its basic two-chip version it directly provides four channels of DDR memory, giving 8. The memory latency increases by 25 nanoseconds from 80 ns due to the expanders.
Eight independent links went to the PCI-X and other peripheral devices e. HP's first high-end Itanium chipset was sx, launched in mid with the Integrity Superdome flagship server. It has two independent front-side buses, each bus supporting two sockets, giving The above components form a system board called a cell.
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